The use of the one device cell, invented by Dennard in 1967 (see generally, U.S. Pat. No. 3, 387,286, issued to R. H. Dennard on Jun. 4, 1968, entitled “Field Effect Transistor memory”), revolutionized the computer industry, by significantly reducing the complexity of semiconductor memory. This enabled the cost, of what was then a scarce commodity, to be drastically reduced.
Today, dynamic random access memories (DRAMs) are a mainstay in the semiconductor industry. DRAMs are data storage devices that store data as charge on a storage capacitor. A DRAM typically includes an array of memory cells. Each memory cell includes a storage capacitor and an access transistor for transferring charge to and from the storage capacitor. Each memory cell is addressed by a word line and accessed by a bit line. The word line controls the access transistor such that the access transistor controllably couples and decouples the storage capacitor to and from the bit line for writing and reading data to and from the memory cell.
Over the course of time what was a very simple device (a planer capacitor and one transistor) has, because of even shrinking dimensions, became a very complex structure, to build. Whether it is the trench capacitor, favored by IBM, or the stacked capacitor, used by much of the rest of the industry, the complexity and difficulty has increased with each generation. Many different proposals have been proposed to supplant this device, but each has fallen short because of either the speed of the write or erase cycle being prohibitively long or the voltage required to accomplish the process too high. One example of the attempt to supplant the traditional DRAM cell is the so-called electrically erasable and programmable read only memory (EEPROM), or more common today, flash memory.
Electrically erasable and programmable read only memories (EEPROMs) provide nonvolatile data storage. EEPROM memory cells typically use field-effect transistors (FETs) having an electrically isolated (floating) gate that affects conduction between source and drain regions of the FET. A gate dielectric is interposed between the floating gate and an underlying channel region between source and drain regions. A control gate is provided adjacent to the floating gate, separated therefrom by an intergate dielectric.
In such memory cells, data is represented by charge stored on the polysilicon floating gates. The charge is placed on the floating gate during a write operation using a technique such as hot electron injection or Fowler-Nordheim (FN) tunneling. Fowler-Nordheim tunneling is typically used to remove charge from the polysilicon floating gate during an erase operation. A flash EEPROM cell has the potential to be smaller and simpler than a DRAM memory cell. One of the limitations to shrinking a flash EEPROM memory cell has been the requirement for a silicon dioxide gate insulator thickness of approximately 10 nm between the floating polysilicon gate and the silicon substrate forming the channel of a flash field effect transistor. This gate thickness is required to prevent excess charge leakage from the floating gate that would reduce data retention time (targeted at approximately 10 years).
Current n-channel flash memories utilize a floating polysilicon gate over a silicon dioxide gate insulator of thickness of the order 100 Å or 10 nm in a field effect transistor. (See generally, B. Dipert et al., IEEE Spectrum, pp. 48-52 (October 1993). This results in a very high barrier energy of around 3.2 eV for electrons between the silicon substrate and gate insulator and between the floating polysilicon gate and silicon oxide gate insulator. This combination of barrier height and oxide thickness results in extremely long retention times even at 250 degrees Celsius. (See generally, C. Papadas et al., IEEE Trans. on Electron Devices, 42, 678-681 (1995)). The simple idea would be that retention times are determined by thermal emission over a 3.2 electron volt (eV) energy barrier, however, these would be extremely long so the current model is that retention is limited by F-N tunneling off of the charged gate. This produces a lower “apparent” activation energy of 1.5 eV which is more likely to be observed. Since the retention time is determined either by thermal excitation of electrons over the barrier or the thermally assisted F-N tunneling of electrons through the oxide, retention times are even longer at room temperature and/or operating temperatures and these memories are for all intensive purposes non-volatile and are also known as non volatile random access memories (NVRAMs). This combination of barrier height and oxide thickness tunnel oxide thickness is not an optimum value in terms of transfer of electrons back and forth between the substrate and floating gate and results in long erase times in flash memories, typically of the order of milliseconds. To compensate for this, a parallel erase operation is performed on a large number of memory cells to effectively reduce the erase time, whence the name “flash” or “flash EEPROM” originated since this effective erase time is much shorter than the erase time in EEPROMs.
P-channel flash memory cells, as shown in FIG. 1A having gate oxide thicknesses of approximately 100 Å, have been reported (see generally, T. Ohnakado et al., Digest of Int. Electron Devices Meeting, Dec. 10-13, 1995, Washington D.C., pp. 279-282; T. Ohnakado et al., Digest of Int. Electron Devices Meeting, Dec. 8-11, 1996, San Francisco, pp. 181-184; T. Ohnakado et al., Proc. Symposium on VLSI Technology, Jun. 9-11, 1998), Honolulu, Hi., pp. 14-15) and disclosed (see U.S. Pat. No. 5,790,455, issued Aug. 4, 1998, entitled “Low voltage single supply CMOS electrically erasable read-only memory”). These reported and disclosed p-channel flash memory cells which work similar to n-channel flash memory cells in that they utilize hot electron effects to write data on to the floating gate. If the magnitude of the drain voltage in a PMOS transistor is higher than the gate voltage, then the electric field near the drain through the gate oxide will be from the gate (most positive) towards the drain (most negative). This can and will cause hot electrons to be injected into the oxide and collected by the gate as shown in FIG. 1B. The mechanisms reported are either channel hot electron injection, CHE, or band-to-band tunneling induced hot electron injection, BTB. The gate current in PMOS transistors (see generally, I. C. Chen et al., IEEE Electron Device Lett. 4:5, 228-230 (1993); and J. Chen et al., Proceedings IEEE Int. SOI Conf., Oct. 1-3, 1991, pp. 8-9) can actually be much higher than the gate current in NMOS transistors (see generally, R. Ghodsi et al., IEEE Electron Device Letters, 19:9, 354-356 (1998)) due to the BTB tunneling. Negatively, higher gate current in the PMOS transistors resulting from this BTB tunneling effect limits the reliability of deep sub-micron CMOS technology, as reported by R. Ghodsi et al. In other words, the reliability of the PMOS array is lowered because of this higher current in the PMOS device.
In addition to these hot electron effects for electron injection and tunneling through the gate oxide, there is of course also the usual Fowler-Nordheim (FN) tunneling and band-to-band tunneling, BTB, which can and has been used to write and erase conventional tunneling mode n-channel flash memory cells. In the case of p-channel devices with heavily doped p-type source and drain regions where there are no electrons available for tunneling in the conduction band, valence band electrons can tunnel through the gate oxides or insulators. (See generally, C. Salm et al., IEEE Electron Device Letters, 19:7, 213-215 (1998)). In this latter case, the energy barrier is higher which makes the tunneling probability lower. To account for this drawback, silicon germanium (SiGe) floating gates have been used to reduce this barrier. FIGS. 2A and 2B illustrate one of the primary reliability concerns in CMOS technology and in flash memory technology. This is the concern of electrons being injected into the silicon substrate with energies over 4.7 eV. These electrons can generate electron hole pairs and the “hot holes” can be injected back into the silicon oxide gate insulator. “Hot hole” injection will lead to reduced barriers for electrons, localized high currents and p-channel threshold voltage shifts. FIG. 2B illustrates the threshold voltage shift on a high frequency MOS capacitance vs. voltage (C-V) curve. Such threshold voltage shifts are undesirable in flash memory devices. This is one of the reasons n-channel flash memories use source side tunneling erase, to avoid the build up of trapped holes and/or anomalous positive charge in the transistor gate oxide above the channel.
There is a need in the art to develop p-channel floating gate transistors which can be implemented in deep sub-micron CMOS technology devices, i.e. which can replace DRAM cells in CMOS technology. That is, it is desirable to develop p-channel floating gate transistors which are more responsive, providing faster write and erase times than conventional Flash Memory. It is further desirable that such p-channel floating gate transistors are more reliable, e.g. avoid p-channel threshold voltage shifts and achieve source side tunneling erase.